Design-for-Test (DFT) & ATPG Engineer

Job Overview:

We are looking for a DFT and ATPG specialist to contribute to the development and validation of digital test methodologies. The ideal candidate will have experience in scan chain design, fault modeling, and test pattern generation, with a strong understanding of industry-standard DFT architectures and techniques.

Key Responsibilities:

• Develop and implement design-for-test strategies including JTAG (1149.1, 1149.6, 1687), IEEE 1500, scan chains, and logic BIST.
• Work with JTAG/1500/1687 test infrastructures, including writing and interpreting BSDL, ICL, and PDL files.
• Optimize test compression, on-chip clocking, and apply various logic fault models (e.g., stuck-at, transition, bridging, cell-aware, timing-aware fault models).
• Perform scan insertion, automatic test pattern generation (ATPG), coverage analysis, and pattern validation to ensure high fault detection.
• Utilize Cadence Modus/Genus or Mentor Tessent/MBIST Architect for test implementation and validation.
• Develop automation scripts using TCL, Python, or Perl to enhance test and verification workflows.
• Collaborate on post-silicon validation, including pattern conversion for ATE, silicon bring-up, debug, and characterization.
• Work closely with backend design teams on aspects like timing analysis, clock domain crossing (CDC), and chip integration.
• Apply memory BIST (MBIST) techniques, including test algorithms and IO loopback strategies.

Preferred Skills & Experience:

• Expertise in digital test methodologies and DFT feature implementation.
• Strong working knowledge of fault modeling and ATPG techniques.
• Hands-on experience with DFT tools from major EDA vendors.
• Proficiency in scripting languages for automation.
• Experience in post-silicon debug, ATE pattern validation, and silicon characterization is beneficial.
• Exposure to backend chip design flows, timing closure, and advanced MBIST architectures is an added advantage.